1. Field of the Invention
This invention relates to the field of computer aided design for digital circuits, particularly to linking results from a logic synthesis system to a behavioral synthesis system.
2. Statement of the Related Art
Behavioral Synthesis
Behavioral vs. Register Transfer Level Design
Many of today's integrated circuits are described using a Hardware Description Language (HDL). Two common HDL's are VHDL and Verilog. VHDL is described in the IEEE Standard VHDL Language Reference Manual available from the Institute of Electrical and Electronic Engineers in Piscataway, N.J. which is hereby incorporated by reference. Verilog is described in The Verilog Hardware Description Language by Donald E. Thomas and Philip Moorby, Kluwer Academic Publishers, 1991 which is hereby incorporated by reference.
As integrated circuits become increasingly complex, hardware designers are increasingly using synthesis software to transform HDL descriptions of digital circuits into mapped logic. The designer writes a description of a digital circuit in VHDL, Verilog, or another HDL, and uses synthesis software to create a digital circuit from the description. Using synthesis software typically shortens the amount of time required create a digital circuit from a design specification, and allows a designer to create more complex designs than is possible manually.
Many of today's complex designs are expressed as software descriptions and simulated to verify their correctness. These designs are later translated from software into hardware, in the form of Integrated Circuits (ICs), Application Specific Integrated Circuits (ASICs), or Field Programmable Gate Arrays (FPGAs), for implementation in the final product. This design description methodology is called algorithmic-level design.
Instead of beginning design at the Register Transfer Level (RTL), behavioral synthesis begins at the algorithmic (behavioral) level. RTL level design is described in Computer Structures: Reading and Examples by C. Gorden Bell and Allen Newell, McGraw-Hill 1971. A behavioral hardware description language (HDL) specification contains instructions, operations, variables, and arrays similar to the original software algorithm.
The target architecture of behavioral synthesis is a general computing model that contains datapath, memory, and control elements. Conventional design techniques currently use a manual RTL design methodology to build a datapath. A datapath is a sequence of logic consisting of registers, higher order functional units (such as adders and multipliers), and multiplexers. The datapath in a digital circuit uses the circuit's inputs to compute output results. Registers are 1-bit memory elements which hold their value through each clock cycle.
Conventional design techniques also build a controller at the RTL to sequence and control the actions of the datapath, memory, and Input/Output (I/O). Frequently, such controllers are implemented using a Finite State Machine (FSM). Finite state machines are described in Switching and Finite Automata Theory by Zvi Kohavi, Computer Science Press, 1978 which is hereby incorporated by reference. Controllers may also determine actions such as which branch of a conditional statement is executed.
Behavioral synthesis builds this architecture by using automated methods of scheduling, allocation, register sharing, memory and control inferencing--all of which are performed manually in an RTL methodology. The designer is freed from having to specify the exact architecture of a design and can automatically explore many implementations to find the optimal architecture.
Components of Behavioral Synthesis
The High-Level Synthesis of Digital Systems by Michael McFarland, Alice Parker, and Raul Camposano, in Proceedings of the IEEE, February 1990, which is hereby incorporated by reference, provides an excellent overview of High Level Synthesis, as Behavioral Synthesis is often called.
Three components of a behavioral synthesis system are Scheduling, Allocation, and Resource Sharing.
Scheduling determines in which clock cycle each operation executes. Scheduling extracts the control and data flow operations of a design specification and assigns these operations to cycles. A state machine controller is synthesized to sequence the operations and execute them in their assigned cycle. The typical goal of this process is to assign operations to cycles so as to be able to implement the design with the fewest resources (registers, multiplexers, and operations) while at the same time minimizing the number of clock cycles (latency).
Allocation is a behavioral synthesis task that maps the operations and data of a behavioral HDL specification into the datapath, which contains memories, registers, functional units such as adders and multiplexers, and gates. Allocation determines which type of operation to use for each operator. For instance, if an operator performs addition, a ripple carry, a carry-lookahead, or some other type of adder can be used.
Resource Sharing attempts to share hardware resources between operators in a design. For example, consider two additions which occur in mutually exclusive conditional branches. Such additions will never be performed at the same time. Thus, they can be performed on the same piece of hardware. Resource sharing attempts to minimize the amount of hardware used by sharing hardware as much as possible.
Estimating Delays
Behavioral transformations such as scheduling require delay information. Conventional behavioral synthesis systems use estimates for operation delays. Two common methods are use of unit delays for operations, and use of an operation library which contains timing information. Systems which use unit operation delays assume that an operation will require a unit amount of time to complete. For instance, a ripple carry adder is assumed to have a delay of 5. This method is used in many systems to estimate delays for actual elements. It is simple to implement, and does not require actual timing measurements on the circuit. However, this method does not provide accurate timing estimates for real circuits.
Timing information in operation libraries is more accurate than unit delays. Operation libraries typically contain different types of operations with different bit widths. Each operation in the library contains timing information which has been generated by a timing verifier. The timing information for each operation is reasonably accurate for that bit width of that particular type of operation. Due to computer storage requirements, operation libraries do not include every possible type of operation in every possible bit width. Systems which use operation libraries must interpolate or extrapolate when the correct operation in the correct bit width is not available. Furthermore, operation libraries do not include chained timing information. Chained timing information gives the total delay for two or more serially connected operations. Operation libraries also lack timing information for control chaining as well as for combinational logic that can also be serially connected to operations.
Control Chaining
When neither the inputs nor the outputs of a control FSM are registered, the control FSM can possibly use a datapath result to generate a control signal that controls some other action of the datapath all within a single cycle. For example, a controller may need to generate a signal to drive a multiplexer that controls which branch of a conditional is executed. The control signal must be generated before the operations driven by the multiplexer can execute. If the clock cycle is sufficiently long, the control signal can be generated, and then the datapath operation(s) can be executed in the same clock cycle. This is called control chaining since the calculation of the control signals has been chained into the same cycle as datapath operations.
Multicycle Constraints
Some operations, such as large multipliers, may require multiple cycles to create valid outputs. Such operations are called multicycle operations. When the datapath is manually specified at the RTL level, the designer must specify all of the multicycle paths in the design to the logic synthesis system. This specification is necessary so that the logic synthesizer does not try to optimize the multicycle paths so that they can execute in a single cycle.
Because each possible path must be enumerated, manual specification of multicycle constraints is tedious and error prone. For example, consider a 32 bit by 32 bit multiplier. Such a multiplier produces 64 bits of output. There are (32+32)*64=4096 possible paths through this multiplier. Each of these paths must be individually annotated to ensure that logic synthesis performs properly.